Configuring the MIG 7 Series IP to Use the DDR Memory on Digilent's Nexys 4 Board

Introduction: Configuring the MIG 7 Series IP to Use the DDR Memory on Digilent's Nexys 4 Board

This tutorial is the second part of a three part series that deals with setting up the MIG IP provided by Xilinx to use the DDR memory on board the Nexys4 Board and interface it with the AXI TFT IP to use the VGA port on the board.

Please make sure you have configured the MIG for use with the board that you are using. If you haven't, please follow the first tutorial and configure the DDR2 memory on the Nexys4.

Double click the MIG core and configure it by following the next few steps

Step 1: Double-click the MIG 7 Series IP. the Memory Interface Generator Wizard Opens. Click Next.

Step 2: By Default, the IP Integrator Enables the Create Design Option, and Sets the Number of Controllers to 1. Ensure That the AXI4 Interface Checkbox Is Checked, and Click Next.

Step 3: In the Pin Compatible FPGAs Page, Select Nothing, and Click Next.

Step 4: In the Next Page, DDR3 SDRAM Memory Is Checked by Default, We're Setting Up the DDR2 Memory, So Select It and Click Next.

Step 5: Set the Value of the Clock Period to 3077 Ps (324.99 MHz). Make Sure the Memory Part Is MT47H64M16HR-25E and Click Next

Step 6: In the AXI Parameters Options Page Do the Following:

• Set Data Width to 64.

• Set Narrow Burst Support to 1.

• Click Next.

Step 7: In the MIG Memory Options Page:

• Set the Input Clock Period to 5000 ps (200 MHz) RTL (nominal)

• Click Next.

Step 8: On the MIG System Clock Page, Set the Reference Clock Configuration to Use System Clock. Change System Reset Polarity to ACTIVE LOW, and Click Next

Step 9: In the MIG Internal Termination for High Range Banks Page, Make Sure the Internal Termination Impedance Is 50 Ohms. Click Next.

Step 10: In the MIG Pin/Bank Selection Mode Page, Select Fixed Pin Out. Click Next.

Step 11: You Next Import the Pin Configurations a Specified User Constraint File (UCF). for That, Download the File Given Here.


Step 12: In the MIG Pin Selection for Controller Page, Click Read XDC/UCF. Navigate to the Folder Where You Unzipped and Placed the Mig.ucf, and Click Open to Import the File.

Step 13: Click Validate to Validate the Pinout

Step 14: You See a DRC Validation Log Dialog Box, Stating That the Current Pinout Is Valid. Click OK. After Reviewing the Message, Click Next.

Step 15: In the Systems Signal Selection, Make Sure You Have the System Clock Pin Selection As Shown in the Figure.

Step 16: Click Next to Open a Summarized Report

Step 17: Click Next to Open the Simulation Model License Agreement.

Step 18: Click Accept to Accept the License Agreement.

Step 19: Click Next to Open a PCB Configuration Note.

Step 20: Click Next. the Design Notes Open.

Step 21: Click Generate to Generate the Mig_7_series DDR2 IP.

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    5 Discussions


    2 years ago

    Hi Akshar,

    I am using vivado 2016.1, I am trying to generate MIG ddr2 example design, i have given input clock as 200 Mhz and my DDR clock is 300 Mhz, I able to generate bitstream file with debug file but whenever i burn it on the board(Nexsys4 ddr) it gives me as Mismatch in debug file and source file.

    Another thing which I am not clear is about the board's crystal clock which is 100Mhz, how can we give this as input clock to the mig since it is expecting 200 Mhz if suppose i have clock wizard the mig is throwing error in the implementation phase.


    Reply 2 years ago

    Do you wish to know how to access this memory?


    Reply 2 years ago

    I have created that ip. But what to do next to access that DDR2 memory. I want to use that memory as a rom that will store a matrix. From that i will read a column at a time. Reading should be done at 100Mhz. Data width of 11bit is enough.
    Can you plz proviide me some manual how to do this.


    4 years ago

    Really interesting and useful information!