This tutorial is the second part of a three part series that deals with setting up the MIG IP provided by Xilinx to use the DDR memory on board the Nexys4 Board and interface it with the AXI TFT IP to use the VGA port on the board.
Please make sure you have configured the MIG for use with the board that you are using. If you haven't, please follow the first tutorial and configure the DDR2 memory on the Nexys4.
Double click the MIG core and configure it by following the next few steps
Step 1: Double-click the MIG 7 Series IP. the Memory Interface Generator Wizard Opens. Click Next.
Step 2: By Default, the IP Integrator Enables the Create Design Option, and Sets the Number of Controllers to 1. Ensure That the AXI4 Interface Checkbox Is Checked, and Click Next.
Step 3: In the Pin Compatible FPGAs Page, Select Nothing, and Click Next.
Step 4: In the Next Page, DDR3 SDRAM Memory Is Checked by Default, We're Setting Up the DDR2 Memory, So Select It and Click Next.
Step 5: Set the Value of the Clock Period to 3077 Ps (324.99 MHz). Make Sure the Memory Part Is MT47H64M16HR-25E and Click Next
Step 6: In the AXI Parameters Options Page Do the Following:
• Set Data Width to 64.
• Set Narrow Burst Support to 1.
• Click Next.
Step 7: In the MIG Memory Options Page:
• Set the Input Clock Period to 5000 ps (200 MHz) RTL (nominal)
• Click Next.
Step 8: On the MIG System Clock Page, Set the Reference Clock Configuration to Use System Clock. Change System Reset Polarity to ACTIVE LOW, and Click Next
Step 9: In the MIG Internal Termination for High Range Banks Page, Make Sure the Internal Termination Impedance Is 50 Ohms. Click Next.
Step 10: In the MIG Pin/Bank Selection Mode Page, Select Fixed Pin Out. Click Next.
Step 11: You Next Import the Pin Configurations a Specified User Constraint File (UCF). for That, Download the File Given Here.