Introduction: Making a Charge Redistribution SAADC in Falstad Circuit Simulator

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The Falstad Circuit Simulator is a simple, easy-to-use, browser-based analogue and digital simulator which is useful for testing ideas and proving basic circuits. It includes a large library of example circuits making it a great resource for learning about analogue and digital electronics. It can be a powerful tool to aid discussions as it can generate links to a circuit for sharing.

The simulator is interactive in the sense that some components like switches can be toggled during the simulation, some component parameters can be controlled via sliders in the user interface and any circuit can be easily modified. The ability to modify the circuit while the simulation is running is an unusual feature.

For analogue to digital converters the simulator includes examples for a Flash ADC, a Delta-Sigma ADC and a "Half-Flash" (subranging/pipelined) ADC. This article shows one way to create a Successive Approximation ADC (SAADC) using the switched-capacitor / charge redistribution design. This design is commonly used for 12bit ADCs in microcontrollers, for example the Nordic nRF52 series, the Raspberry Pi RP2040 and STMicroelectronics STM32 series.

The concept of performing a binary search by repeatedly comparing a register's digital-to-analogue converter (DAC) output value to a (stable) analogue input value is fairly straightforward, but the efficient implementation using charge redistribution is more complex and is rarely explained in detail. The simulator allows this to be clearly seen and the simulation speed can be adjusted for a slower view of the conversion steps. The example shown in this article only has three bits but this is enough to show the principle of operation.

This article was inspired by the search for a good explanation of SAADC operation for Exploring and Reducing ADC Noise on Adafruit CLUE (Nordic NRF52840).

Supplies

  • Just a web browser!

Step 1: Basic Principle

The successive approximation ADC Wikipedia page has a simple block diagram (above) showing the main components of this type of ADC. The input voltage is compared with the analogue output of the DAC based on the successive approximation register (SAR) value. The input voltage needs to be stable for the comparisons to be valid. This is achieved with a sample and hold (S/H) component.

The most efficient algorithm for an unpredictable input value is to perform a binary search. This is similar to a well-played higher lower number guessing game. An example of a binary search for a 3bit resolution ADC with a Vref of 8V and Vin of 3.30V is shown below.

  1. SAR=100, is Vin greater than or less than 4V (Vref/2)? It's less than, D2=0.
  2. SAR=010, is Vin greater or less than 2V (Vref/2 - Vref/4)? It's greater than, D1=1.
  3. SAR=011, is Vin greater or less than 3V (Vref/2 - Vref/4 + Vref/8)? It's greater than, D0=1.

The end of conversion (EOC) output indicates the value has been converted and the register value of 011 (3 in decimal) now represents the quantised 3.30V input voltage.

Step 2: The Components

This is an example of a successive approximation analogue to digital converter using the charge redistribution design with binary-weighted, switched capacitors.

The sections of the ADC are shown above and described below.

  1. Control/sequencing logic - a sixteen step logic sequencer driven by a clock with some additional logic to enable setting capacitor switches based on output values.
  2. Switched capacitors - s1 (msb) to s3 (lsb) plus s4, the heart of the charge distribution ADC. The capacitance values are a series with values: C/2, C/4, C/8 and another C/8 to give a total capacitance of C.
  3. Voltage references - there are two options to enable exploration of the boundary values for conversion. This is discussed on the next page.
  4. Shift Register and latch - the shift register is a serial to parallel converter, these are used to store and hold the digital output value. A buffer is required to delay the clock to the shift register to align it with the CREAD output from the sequencer. There is some redundancy here, the converted output value is also present on the switch positions at the end of the conversion.
  5. Acquisition/discharge switches - two voltage sources are provided for demonstration, a sine wave and a set voltage. The switches are labelled sA and sB here, respectively. Diagrams elsewhere may use the same notation for different roles or may use 3 way switches for each capacitor.
  6. Comparator - calculates the output bit for each step in the binary search.
  7. Visualisation aids - this part of the circuit is not part of the ADC, it just provides outputs for the simulator's plotter and the LEDs to provide a visual guide indicating the processing step.

A real SAADC will differ from this simple example created by a novice.

  • It will typically have around 11-13 bits for microcontrollers and more specialised ones may be 8-18bits. The Analog Devices AD7641 is an example of an 18bit SAADC.
  • It may have a more optimal design!
  • It's likely to feature some degree of pipelining to offer improved sampling rates and more continuous sampling.
  • It will have features that enable a runtime calibration process which improves the accuracy particularly with temperature changes.
  • It may have an optional over-sampling features to trade-off sample rate for an improvement in the accuracy (ENOB).
  • The total capacitance of the capacitor array (8pF) may be lower but this is simply set by scaling the capacitor values. The RP2040 data sheet states the input capacitance of its ADC is "about 1pF" in section 4.9.2.
  • There may be a choice of reference voltages and an amplifier (which may attenuate) on the ADC input for more flexibility on the voltage range.

Step 3: SAADCing

This is an example using the same sine wave used for the Flash ADC example in Exploring and Reducing ADC Noise on Adafruit CLUE (Nordic NRF52840). Many of the control lines and the red LEDs here are visually misleading as their rapid changing is faster than the frame rate of the animated gif. As can be seen, there is a lot more going on inside an SAADC compared to a Flash ADC.

The output for this type of ADC is driven by the clocked sequencer making it produce values inherently in discrete time. For comparison, the Flash ADC only has a minimum amount of time for a stable value to be produced determined by the speed of the comparators and gate delays in the layer of logic gates.

The upper and lower voltage references are set to -0.5V and 7.5V. This gives the same mapping as the Flash ADC example where the input voltage is mapped to the nearest ADC code. Most examples would use 0V and 8V but this will implement a round down approach, i.e. 0.99V would be converted to 0. The difference becomes increasing small with higher resolutions. The gang switches for the voltage references can be manually flipped to experiment with this.

The simulator indicates positive voltages with green and negative voltages with red. The current visualisation is turned off for this circuit as it's not particularly informative for an ADC. It can be enabled to watch the charge flow between capacitors during the conversion.

Step 4: Inside the Control Unit

The 4bit counter's Q0-Q3 outputs (far left of circuit) drive the I0-I3 inputs of a custom logic component which has an (in-order) mapping shown below. The outputs A, S1GND, S2GND, S3GND, S4GND, S1D, S2D, S3D, S4D, S1IN, S2IN, S3IN, S4IN, CREAD, B, LAT are controlled by this mapping.

0000=0000000001111010   sample
0001=0000000000000010   sample
0010=0000000000000010   sample
0011=0000000000000000   sample
0100=1000000000000000   convert
0101=1111100000000000   convert
0110=1000000001000000   convert bit 2 (msb)
0111=1000010000000100   convert bit 2
1000=1000000000100000   convert bit 1
1001=1000001000000100   convert bit 1
1010=1000000000010000   convert bit 0 (lsb)
1011=1000000100000100   convert bit 0
1100=0111100000000011   output & discharge
1101=0111100000000010   discharge
1110=0111100000000010   discharge
1111=0111100000000010   discharge

There are some repeats in this sequence. This is mainly due to having spare steps in the 16 steps to fill. A real implementation may use a similar approach for operations which take multiple clock cycles. The clock is only running at 100kHz - a real ADC will have more steps and run at MHz rates.

The counters in the Falstad Circuit Simulator start at 1 when the simulator is first started rather than 0. The push button can be used to reset it to 0.

Step 5: A Single Conversion

This is a closer look at a single conversion. The input voltage fluctuates but at the end of the sampling period rests at 5.3V. For a real ADC, the source impedance of the device connected to the analogue input needs to be low enough to fully charge the capacitor array within the sampling time. This acquisition time may be configurable to offer some flexibility.

The conversion steps are:

  1. Sample acquisition, the final value is 5.3V. The comparator input is Vref - 5.3V = 2.7V. The input voltage drops later to 1.5V during conversion but the 5.3V has been held allowing the conversion to proceed correctly.
  2. The capacitor switches are all set to the lower voltage reference, signal ground in this case.
  3. s1 is set to Vref, comparator input is -1.3V (Vref/2 - 5.3) therefore bit2 (msb) = 1 and switch remains unchanged.
  4. s2 is set to Vref, comparator input is 0.7V (Vref/4 + Vref/2 - 5.3) therefore bit1 = 0 and switch reverts.
  5. s3 is set to Vref, comparator input -0.3V (-Vref/8 + Vref/4 + Vref/2 - 5.3) therefore bit1 (lsb) = 1 and switch remains unchanged. This final comparator output indicates the error from the ADC's quantisation process.
  6. The output value 101 is latched and the discharge of the capacitor array starts.

Step 6: Charge Redistribution Across Capacitors

This is a simple circuit to allow the reader to play with charge redistribution. It's not intended to model any particular part of an SAADC. The top capacitor is referred to here as C1 and the one below it as C2. C1 and C2 have a potential difference of V1 and V2 and charge Q1 and Q2. The voltages cited here are from top to bottom.

The simulator shows the flow of conventional current with the movement of the yellow dots representing the charge. Its plotter is showing the two voltages V1+V2 in red and V2 in green.

  1. Everything starts at 0V, the capacitors are uncharged.
  2. The switches change and 2V is connected to the middle terminal between the capacitors with the opposite terminal grounded, both start charging and eventually reach V1=-2V and V2=2V. The charge is Q=CV, the fully charged capacitors will have Q1=-2uC (-2 microcoulombs) and Q2=2uC. The capacitors in this configuration are in parallel. They are visually a little misleading as they can give the false impression of being in series.
  3. The switches change to leave everything disconnected, the (ideal) capacitors maintain their charge and the voltages that were applied across them.
  4. The switch changes and middle terminal becomes unconnected and 6V is applied across the two capacitors. The increase in voltage from 0V to 6V will cause charge to flow across the two capacitors in series. After 3uC has flowed voltage equilibrium is achieved at Q1=-2 + 3=1uC and Q2=2uC+3uC =5uC. The V1 = 1uC/1uF = 1V, V2=5uC/1uF = 5V.
  5. The switches change to leave everything disconnected.
  6. The push button connects the top terminal of C1 to ground. The voltage drops from 6V to 0V now causing charge to flow to upwards and after 3uC has flowed the charge is Q1=1uC-3uC=-2uC and Q2=5uC-3uC=2uC restoring the V1 and V2 to -2V and 2V.
  7. The other push button is pressed grounding the middle terminal. C2 fully discharges as both terminals are now connected to ground. C1 maintains its -2uC charge and V1 is still -2V, with the middle terminal at 0V this leaves the top terminal at -2V. The red line on the plotter falls to -2V as the voltage across V2 is 0.

Step 7: Going Further

The examples under the Circuits menu in the Falstad Circuit Simulator are well worth exploring. It can be used for more than microelectronics, the mains-powered 3 Way Light Switch (commonly found in homes) example is shown above with the resistor replaced by an incandescent light bulb. The simulation happens to be running slow enough to see the bulb warm up and cool down.

Related projects:

Microcontroller simulators:

Further reading: