Introduction: How Does Challenges of Power Supply Design Meet by DC-DC Technologies
I will analyse how does the challenge power supply design meet by DC-DC Technologies.
Power system designers are facing constant pressure from the market to find ways to make the most of available power. In portable devices, higher efficiency extends battery life and puts more functionality into smaller packages. In servers and base stations, efficiency gains can directly save infrastructure (cooling systems) and operating costs (electricity bills). To meet market demands, system designers are improving power conversion processes in multiple areas, including more efficient switching topologies, package innovations, and new semiconductor devices based on silicon carbide (SiC) and gallium nitride (GaN).
Step 1: Improvement of Switching Converter Topology
To take full advantage of available power, people are increasingly adopting designs based on switching technology rather than linear technology. The switching power supply (SMPS) has an effective power of over 90%. This extends the battery life of portable systems, reduces the cost of electricity for large equipment, and saves space previously used for heat sink components.
Switching to a switched topology has certain drawbacks, and its more complex design requires designers to have multiple skills. Design engineers must be familiar with analog and digital technologies, electromagnetics, and closed-loop control. Designers of printed circuit boards (PCBs) must pay more attention to electromagnetic interference (EMI) because high frequency switching waveforms can cause problems in sensitive analog and RF circuits.
Prior to the invention of the transistor, the basic concept of switched-mode power conversion was proposed: for example, the Kate-type inductive discharge system invented in 1910, which used a mechanical vibrator to implement a flyback boost converter for an automotive ignition system.
Most standard topologies have been around for decades, but that doesn't mean engineers don't adjust standard designs to accommodate new applications, especially control loops. The standard architecture uses a fixed frequency to maintain a constant output voltage by feeding back part of the output voltage (voltage mode control) or controlling the induced current (current mode control) under different load conditions. Designers are constantly improving to overcome the flaws of the basic design.
Figure 1 is a block diagram of a basic closed loop voltage mode control (VMC) system. The power stage consists of a power switch and an output filter. The compensation block includes an output voltage divider, an error amplifier, a reference voltage, and a loop compensation component. A pulse width modulator (PWM) uses a comparator to compare the error signal to a fixed ramp signal to produce an output pulse sequence that is proportional to the error signal.
Although the different loads of the VMC system have strict output rules and are easy to synchronize with the external clock, the standard architecture has some drawbacks. Loop compensation reduces the bandwidth of the control loop and slows down the transient response; the error amplifier increases the operating current and reduces efficiency.
The constant on-time (COT) control scheme provides good transient performance without loop compensation. The COT control uses a comparator to compare the regulated output voltage to the reference voltage: when the output voltage is less than the reference voltage, a fixed on-time pulse is generated. At low duty cycles, this causes the switching frequency to be very high, so the adaptive COT controller generates an on-time that varies with the input and output voltages, which keeps the frequency almost constant at steady state. Texas Instrument's D-CAP topology is an improvement over the adaptive COT approach: the D-CAP controller adds a ramp voltage to the feedback comparator input, which improves jitter performance by reducing the noise band in the application. Figure 2 is a comparison of the COT and D-CAP systems.
Figure 2: Comparison of standard COT topology (a) and D-CAP topology (b) (Source: Texas Instruments) There are several different variants of the D-CAP topology for different needs. For example, the TPS53632 half-bridge PWM controller uses the D-CAP+ architecture, which is primarily used in high-current applications and can drive power levels up to 1MHz in 48V to 1V POL converters with efficiencies as high as 92%.
Unlike D-CAP, the D-CAP+ feedback loop adds a component that is proportional to the induced current for precise droop control. The increased error amplifier improves the accuracy of the DC load under a variety of line and load conditions.
The controller's output voltage is set by the internal DAC. This cycle begins when the current feedback reaches the error voltage level. This error voltage corresponds to the amplified voltage difference between the DAC set point voltage and the feedback output voltage.
Step 2: Improve Performance Under Light Load Conditions
For portable and wearable devices, there is a need to improve performance under light load conditions to extend battery life. Many portable and wearable applications are in a low-power "temporary sleep" or "sleep" standby mode most of the time, only activated in response to user input or periodic measurements, so minimize power consumption in standby mode. It is the top priority.
The DCS-ControlTM (Direct Control to Seamless Transition to Energy Saver Mode) topology combines the advantages of three different control schemes (ie, hysteresis mode, voltage mode, and current mode) to improve performance under light load conditions, especially transition to Or when leaving the light load state. This topology supports PWM modes for medium and heavy loads, as well as power saving mode (PSM) for light loads.
During PWM operation, the system operates at its rated switching frequency based on the input voltage and controls the frequency change. If the load current decreases, the converter switches to the PSM to maintain high efficiency until it drops to a very light load. At PSM, the switching frequency decreases linearly with load current. Both modes are controlled by a single control block, so the transition from PWM to PSM is seamless and does not affect the output voltage.
Figure 3 is a block diagram of the DCS-ControlTM. The control loop takes information about the change in output voltage and feeds it directly back to the fast comparator. The comparator sets the switching frequency (as a constant for steady-state operating conditions) and provides an immediate response to dynamic load changes. The voltage feedback loop accurately regulates the DC load. The internally compensated regulation network enables fast and stable operation with small external components and low ESR capacitors.
Figure 3: Implementation of the DCS-ControlTM topology in the TPS62130 buck converter (Source: Texas Instruments)
The TPS6213xA-Q1 synchronous switching power converter is based on the DCS-ControlTM topology and is optimized for high power density POL applications. The typical 2.5MHz switching frequency allows the use of small inductors and provides fast transient response and high output voltage accuracy. The TPS6213 operates from an input voltage range of 3V to 17V and can deliver up to 3A of continuous current between 0.9V and 6V output voltages.